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MC74HCT574A Octal 3-State Noninverting D Flip-Flop with LSTTL-Compatible Inputs
High-Performance Silicon-Gate CMOS
The MC74HCT574A is identical in pinout to the LS574. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. Data meeting the setup time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the states of the flip-flops, but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be stored even when the outputs are not enabled. The HCT574A is identical in function to the HCT374A but has the flip-flop inputs on the opposite side of the package from the outputs to facilitate PC board layout.
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20 PDIP-20 P SUFFIX CASE 738
1
MC74HCT574AN AWLYYWW 1 20
20
20 1
* * * * * * *
SOIC WIDE-20 DW SUFFIX CASE 751D 1 A WL YY WW
HCT574A AWLYYWW
Output Drive Capability: 15 LSTTL Loads TTL NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 286 FETs or 71.5 Equivalent Gates
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device MC74HCT574AN MC74HCT574ADW Package PDIP-20 SOIC-WIDE Shipping 1440 / Box 38 / Rail 1000 / Reel
MC74HCT574ADWR2 SOIC-WIDE
(c) Semiconductor Components Industries, LLC, 1999
1
March, 2000 - Rev. 8
Publication Order Number: MC74HCT574A/D
MC74HCT574A
LOGIC DIAGRAM
D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK OUTPUT ENABLE 2 3 4 5 6 7 8 9 11 1 PIN 20 = VCC PIN 10 = GND 19 18 17 16 15 14 13 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NON- INVERTING OUTPUTS
PIN ASSIGNMENT
OUTPUT ENABLE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLOCK
FUNCTION TABLE
Inputs OE L L L H Clock D H L X X Output Q H L No Change Z
L,H, X
X = don't care Z = high impedance
II I I IIIIIIIIIIIIIII II II IIIIIIIIIIIIIII IIIIIIIIIIIIIII III I I IIIIIIIIIIIIIII IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII IIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIII IIIIIIIIIIIII III I II IIIIIIIIIIIIIII IIIIIIIIIIII
Design Criteria Value 71.5 1.5 5.0 Units ea ns Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product W pJ 0.0075 *Equivalent to a two-input NAND gate.
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MC74HCT574A
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I II I I I II I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I III I I I I I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I I II I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIII I I I IIIIIIIIIIIIIIIIIIIIIII II I I IIII I I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I
II I IIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII II I II I I III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
SymbolIIIIIIIIIIIIII Parameter VCC Vin DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0III V V V - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature Plastic DIP SOIC Package mW Tstg TL - 65 to + 150 260
_C _C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter
Min 4.5 0
Max 5.5
Unit V V
DC Supply Voltage (Referenced to GND)
Vin, Vout TA
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC
- 55 0
+ 125 500
_C
ns
tr, tf
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol VIH VIL
Parameter
Test Conditions
VCC V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5
- 55 to 25_C 2.0 2.0 0.8 0.8 4.4 5.4
v 85_C v 125_C
2.0 2.0 0.8 0.8 4.4 5.4 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4
Unit V V
Minimum High-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v v
Maximum Low-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
VOH
Minimum High-Level Output Voltage
Vin = VIH or VIL |Iout| 20 A
v v v v
Vin = VIH or VIL |Iout| 6.0 mA Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| 6.0 mA
V
3.98 0.1 0.1
3.84 0.1 0.1
VOL
Maximum Low-Level Output Voltage
0.26
0.33
Iin
Maximum Input Leakage Current
Vin = VCC or GND Vin = VCC or GND Iout = 0 A
0.1
1.0
1.0
A
ICC
Maximum Quiescent Supply Current (per Package)
5.5
4.0
40
160
A
1. Output in high-impedance state. NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I I
* Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I III I I I IIII IIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I III I I I I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I
1. Output in high-impedance state.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
TIMING REQUIREMENTS (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Symbol
Symbol
ICC
tr, If
tsu
IOZ
tw
tPZH, tPZL
tPLH, tPHL
tTLH,
fMAX
th
tPLZ, tPHZ
tTHL
CPD
Cin
Maximum Input Rise and Fall Times
Minimum Pulse Width, Clock
Minimum Hold Time, Clock to Data
Minimum Setup Time, Data to Clock
Additional Quiescent Supply Current
Maximum Three-State Leakage Current
Power Dissipation Capacitance (Per Flip-Flop)*
Maximum Input Capacitance
Maximum Output Transition Time, Any Output (Figures 1, 2 and 4)
Maximum Propagation Delay Time, Output Enable to Q (Figures 2 and 5)
Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5)
Maximum Propagation Delay, Clock to Q (Figures 1 and 4)
Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4)
Parameter
Parameter
Parameter
Vin = VIL or VIH (Note 1) Vout = VCC or GND
Vin = 2.4 V, Any One Input Vin = VCC or GND, Other In uts GND Inputs lout = 0 A
Test Conditions
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MC74HCT574A
4 Fig. 1 1 3 3 - 55 to 25_C Min 5.0 15 10 VCC V 5.5 5.5 Max 500 - 55 to 25_C Typical @ 25C, VCC = 5.0 V 10 12 28 28 30 30 - 55 to 25_C - 0.5 Guaranteed Limit - 55_C Min Guaranteed Limit 5.0 19 13 2.9
v 85_C
Guaranteed Limit
v 85_C
v 85_C v 125_C
Max
10
15
35
35
38
24
58
500
- 5.0
25_C to 125_C
Min
5.0
22 15
v 125_C
v 125_C
2.4
- 10
10
18
42
42
45
20
Max
500
MHz
Unit
Unit
mA
A
Unit
pF
pF
ns
ns
ns
ns
ns ns ns ns
MC74HCT574A
EXPANDED LOGIC DIAGRAM
D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9
CLOCK
11 C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q
ENABLE OUTPUT
1
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
SWITCHING WAVEFORMS
tr CLOCK 2.7 V 1.3 V 0.3 V tw 1/fmax tPLH Q 90% 1.3 V 10% tTLH tTHL tPHL Q tf 3.0 V GND OUTPUT ENABLE 1.3 V GND tPZL 1.3 V tPZH Q 1.3 V tPHZ 10% 90% tPLZ HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE 3.0 V
Figure 1.
Figure 2.
TEST POINT
VALID 3.0 V 1.3 V DATA GND tsu th 3.0 V 1.3 V CLOCK GND DEVICE UNDER TEST
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 3.
TEST POINT OUTPUT DEVICE UNDER TEST 1 k
Figure 4. Test Circuit
CL*
CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 5. Test Circuit
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MC74HCT574A
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
11
-A-
20
B
1 10
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
SO-20 DW SUFFIX CASE 751D-05 ISSUE F
D A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
h
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
DIM A A1 B C D E e H h L
L
18X
e
A1
q
T
C
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MC74HCT574A
Notes
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MC74HCT574A
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PUBLICATION ORDERING INFORMATION
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